Clock Synchronization


This project is a basic, self-contained example of synchronizing two clocks (see link for Git repo below). The text here is from the readme, giving a rough explanation of principles.

In many cases it is important to be able to lock the frequency and phase of a clock to a second reference clock. Communications systems are often required to do this to properly receive incoming data. Measurement systems may need to do this to synchronize measurements to an external reference. In my particular case, I am interested in synchronizing a high-speed clock inside an FPGA to a PPS signal from a GPS module, to allow for very accurate timing of an ADC.

Note that this is essentially what a PLL does.

The code in this repository is a very basic example of how two clocks can be made to run in sync. The example is self-contained, in that it requires only an FPGA and a single clock, but this also means it is not entirely complete as the two test clock signals are actually derived from a common source. A more advanced example would use an external free-running clock to show how the slave clock follows dynamic changes in the reference clock.

What this code does:


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